A Delay Locked Loop (DLL) with an adjustable delay line is used to synchronize a first clock signal with a second clock signal by delaying the first clock signal. The DLL includes a phase detector, which detects the phase difference between the first clock signal and the second clock signal. Based on the detected phase difference, the DLL synchronizes the first clock signal to the external clock signal by adding an appropriate delay to the first clock signal until the second clock signal is in phase with the first clock signal.
FIG. 1 is a block diagram of a prior art DLL 100. An externally supplied clock (CLK) is buffered by clock buffer 101 to provide a reference clock (CLK_REF) that is coupled to a voltage controlled delay line 102 and a phase detector 104. The voltage controlled delay line 102 produces an output clock (CLK_OUT), which is a delayed version of CLK_REF and is routed to various circuits within the device and to the replica delay circuit 103. The replica delay circuit 103 provides a delay similar to the delay through buffer 101 and wire routing delays. Replica delays are well-known to those skilled in the art. See commonly owned U.S. Pat. No. 5,796,673 to Foss et al for further explanation of replica delays. A feedback clock signal CLK_FB output from the replica delay circuit 103 is coupled to the phase detector 104. Other prior art DLLs use a digital delay line or a tapped delay line. Commonly owned U.S. Pat. Nos. 5,796,673 and 6,087,868 describe such DLLs
The phase detector 104 generates phase control signals (UP, DOWN) dependent on the phase difference between CLK_REF and CLK_FB. The DOWN signal is set to a logic ‘1’ on each CLK_REF rising edge and the UP signal is set to a logic ‘1’ on each CLK_FB rising edge. Both UP and DOWN signals are reset to logic ‘0’ when the second rising edge of the two signals is received. Thus, when the CLK_REF rising edge is detected before the CLK_FB rising edge, the DOWN signal transitions to a logic ‘0’ to decrease the delay in the voltage controlled delay line (VCDL) 102 until the next rising edge of the CLK_FB is detected. Alternatively, if CLK_FB rising edge is detected prior to the CLK_REF rising edge, the UP signal is asserted (logic ‘1’) to increase the delay until the next rising edge of CLK_REF is detected.
The phase control signals (UP/DOWN) of the phase detector 104 are integrated by a charge pump 105 and a loop filter 106 to provide a variable bias voltage VCTRL 110 for the VCDL 110. The bias voltage VCTRL selects the delay to be added to CLK_REF by the VCDL 102 to synchronize CLK_FB with CLK_REF.                The phase detector 100 may be level sensitive or edge triggered. Typically, edge triggered phase detectors are used because level sensitive phase detectors are susceptible to false locking. However, the clock is free running, and it is not known which clock edge will occur first after a reset. Thus, dependent on the initial phase relationship between the input signals to the phase detector (i.e. dependent on whether the rising edge of the CLK_REF or CLK_FB occurs first after system reset or power up). The UP (DOWN) signal may be triggered first when the delay should be decreased (increased), so DLLs with edge triggered phase detectors may never achieve lock.        
FIG. 2 is a schematic diagram of a prior art edge triggered phase detector 104. The phase detector 104 detects the phase difference between CLK_REF and CLK_FB and sets the UP, DOWN signals to logic ‘1’ dependent on the phase difference to increase or decrease the delay. The phase detector 104 includes two rising edge triggered D-type Flip-Flops (DFF) 201, 203 and a reset circuit 210. The input of each DFF 201, 203 is coupled to VDD and the respective asynchronous reset input of each DFF 201, 203 is coupled to the output (RSTb) of the reset circuit 210. The reset circuit 210 generates a logic ‘0’ on the RSTb signal to reset DFFs 201, 203 when the RESETb signal is at a logic ‘0’ or when both the UP and DOWN signals are at a logic ‘1’.
The clock input of each DFF is coupled to a respective one of the input signals (CLK_REF, CLK_FB), with the clock input of DFF 201 coupled to CLK_REF and the clock input of DFF 203 coupled to CLK_FB. The output of each DFF 201, 203 is coupled to respective UP/DOWN inputs of charge pump 105 (FIG. 1) to increase or decrease the delay of the VCDL 102 based on the detected phase difference between the clocks.
If a rising edge (transition from a logic ‘0’ to a logic ‘1’) of CLK_REF is detected prior to a rising edge of CLK_FB, the delay is decreased. For example, if the rising edge of CLK_REF occurs before the rising edge of CLK_FB, the DOWN signal is asserted (i.e. the output of DFF 201 changes to a logic ‘1’) to decrease the delay. While the DOWN signal is at logic ‘1’, the charge pump and loop filter decrease the delay in the VCDL 102. The DOWN signal remains at a logic ‘1’ until a subsequent rising edge of CLK_FB clocks DFF 203 and the UP signal at the output of DFF 203 transitions from a logic ‘0’ to a logic ‘1’. With both UP and DOWN signals at a logic ‘1’, the reset circuit 210 generates a logic ‘0’ pulse on the RSTb signal. The logic ‘0’ pulse on the RSTb signal coupled to the asynchronous reset inputs of DFF 201, 203 resets DFF 201, 203 and the UP and DOWN signals are reset to a logic ‘0’.
If the rising edge of CLK_FB is detected prior to the rising edge of CLK_REF, the delay is increased, the UP signal transitions from a logic ‘0’ to a logic ‘1’. While the UP signal is at a logic ‘1’, the charge pump and loop filter increase the delay through the delay line. The UP signal is held at a logic ‘1’ until the rising edge of CLK_REF clocks DFF 203 and the DOWN signal transitions to a logic ‘1’. With both UP and DOWN signals asserted (at a logic ‘1’), the reset circuit 210 generates a logic ‘0’ pulse on the RSTb signal and DFFs 201, 203 are reset. After the DFFs 201,203 are reset, the UP and DOWN signals at the outputs of DFFs are reset to a logic ‘0’.                After a power up or system reset, the voltage controlled delay line is typically set to a minimum delay. If after reset or power up, the rising edge of the CLK_REF signal occurs prior to the rising edge of the CLK_FB signal, the phase detector 104 will set the DOWN signal to a logic ‘1’ to decrease the delay. However, the delay will already be at the minimum allowed. Thus, all subsequent phase detector cycles will continue to try to decrease the DLL delay and the DLL will never achieve lock.        
FIG. 3 is a timing diagram that illustrates a clock edge ordering problem after reset. The problem with achieving lock arises when the rising edge of CLK_REF occurs prior to the rising edge of CLK_FB. In the example shown, the rising edge of CLK_REF occurs at the same time as the falling edge of CLK_FB. However, the phase difference is variable and both rising edges may even occur at the same time. FIG. 3 is described in conjunction with the circuit shown in FIG. 2. During reset, the RESETb signal is held at a logic ‘0’ and the delay in the voltage controlled delay line is set to a minimum delay (one unit delay cell). Also, signals UP and DOWN are both held at a logic ‘0’ because DFFs 201, 203 are held reset by a logic ‘0’ on the RESETb signal.
At time 200, the RESETb signal transitions from a logic ‘0’ to a logic ‘1’. As shown, after reset the rising edge of CLK_REF occurs followed by the rising edge of CLK_FB.
At time 202, the first rising edge (from a logic ‘0’ to a logic ‘1’) on the CLK_REF signal sets DFF 201 and the DOWN signal (the output of DFF 201) is set to a logic ‘1’. While the DOWN signal is at a logic ‘1’, the delay in the delay line is decreased. However the DLL delay is already at the minimum value set while RESETb was at a logic ‘0’. Thus, the logic ‘1’ on the DOWN signal has no effect on the delay of VCDL.
At time 204, the rising edge detected on the CLK_FB signal sets DFF 203 resulting in setting the UP signal (the output of DFF 203) to a logic ‘1’. With both the UP signal and the DOWN signal at a logic ‘1’, the reset circuit 210 generates a logic ‘0’ pulse on the RSTb signal to reset both DFFs 201, 203 and the UP and DOWN signals to a logic ‘0’ at time 206.
This sequence is repeated starting with the next rising edge of CLK_REF at time 208 and continues for each subsequent rising edge of CLK_REF and CLK_FB. The delay remains stuck at the minimum delay, and thus, the DLL never achieves lock.